1. Field of the Invention
The present invention relates to switching devices. More particularly, the invention relates to a segmented glitch reduction apparatus for a switching device and a related method of operating the switching device.
This application claims the benefit of Korean Patent Application No. 10-2006-0018521, filed on Feb. 25, 2006, the subject matter of is hereby incorporated by reference.
2. Description of the Related Art
Contemporary electronics increasing include integrated circuits adapted to process both digital and analog signals. This capability is critical to ongoing efforts to reduce the overall size of integrated circuits forming consumer electronic products, such as cell phones. The coincidental processing of both digital and analog signals within a single integrated circuit necessitates the use of a class of high definition circuits referred to as analog-to-digital converters (ADC) and digital-to-analog converters (DAC). A DAC receives one or more digital signal(s), decodes the digital signal, and converts the decoded digital signal into a corresponding analog signal. In so doing, a DAC may adjust an output level of the analog signal in accordance with the input value of the digital signal.
DACs and ADCs are common types of switching circuits. Many switching circuits are segmented in their manner of operation. That is, they process data by dividing it into portions and then processing the data portions separately.
Conventional segmented switching devices have many uses, but also suffer from certain problems. For example, segmented DACs suffer from noise induced errors caused by “glitches.” A glitch is an erroneous signal transition commonly caused, for example, by mistimed data transitions, noisy circuit operations (e.g., flip-flop transitions), external signal interference, etc. Closely related to the effects of common signal (or data) glitches in segmented switching devices are so-called differential nonlinearity (DNL) errors.